1. Field of the Invention
The present invention relates to a logic simulator and a method to simulate logic for use in designing semiconductor integrated circuits, and particularly, large scale integration (LSI).
2. Description of the Related Art
LSI-oriented circuits are generally designed using a computer aided design (CAD) system. To inspect whether a particular circuit design functions properly, a logic simulator incorporated in the CAD system simulates the logic functions of the designed circuit. For example, it is important for a flip-flop circuit, as a sequential circuit, to be subjected to timing simulation including the set-up and hold timing during logic simulation. Accordingly, the logic simulator is also used for the timing simulation. Given the increases in the size and scale of modern LSI circuits, micropatterning and operation speeds, in particular, timing simulation has become an essential simulation tool. It is important, therefore, that logic simulators accurately execute timing simulation.
In general, semiconductor integrated circuits (ICs) are designed using data recorded in a library file (i.e., library data base) provided in the CAD system. The library file holds data of various logic cells. To prepare the library file, a library designer first describes cell design information in a text format by using a circuit editor. This cell design information already includes cell definitions and timing simulation definitions. Each cell definition consists of a net list, i.e., data about the elements the network between the elements forming a logic cell. Each timing simulation definition contains information about a dummy element virtually coupled to one of the elements of a logic cell. This definition forms the basis for the timing simulation.
The application program for preparing library data converts the text data of the cell design information into data in the format that can be handled by the logic simulator. The converted data is registered in the library file.
While designing a logic circuit using the data in the library file, a dummy element is inserted into one cell which needs timing simulation. FIG. 1 exemplifies a designed cell 70. The cell 70 includes an AND gate 71, inverters 72 and 74 and a flip-flop circuit 73. The flip-flop circuit 73 is the target element for which the timing simulation of input signals at its clock pin CK and data pin D should be carried out, and therefore a dummy element 75 is connected in parallel to the pins CK and D. It is to be noted, however, that the dummy element 75 is not normally displayed even when the design of the cell 70 is displayed on the display screen.
In the conventional timing simulation, the logic simulator simulates the timings based on the circuit design data including dummy element data. The conditions used to simulate signal timing at or between the input pins of the dummy element are registered in the logic simulator. When the timing results fail to satisfy predetermined conditions, the logic simulator resolves or attributes this as a timing error.
The conventional timing simulation method requires that the designed data of each cell should previously contain data about the dummy element. The cell must be designed accompanying the dummy element. Consequently, timing simulation is always executed, even during preliminary logic simulation when the initial stage of the proposed logic design is tested to see if the design functions as expected. This reduces the speed of the preliminary logic simulation. Generally speaking, a dummy element is often connected to a circuit element which is relatively frequently driven, such as a clock element in a logic circuit. This therefore increases the burden on the logic simulator.
In addition, each dummy element has its own specific operation, and therefore the number of necessary operations is governed by the number of types of the dummy elements. If an additional simulation item is required for a circuit element, it will be necessary to add another type of dummy element to the circuit element. This addition of dummy elements is disadvantageous in as much as it increases the time necessary to execute the simulation.
Furthermore, the conventional method is applicable only to individual cells, therefore, it is essentially impossible to execute intercell timing simulation. The recent increases in the scale of semiconductor ICs renewed the demand for faster and faster simulation. In this respect, therefore, there is a demand for fast logic simulation absent the element of timing simulation performed at the initial stage of circuit design.
One suggested approach to reduce the amount of data necessary to describe the circuit to be simulated, has been to use truth tables to represent individual cell function. This approach, however, makes it impossible to connect a dummy element to each of the elements incorporated in a cell. Accordingly, as shown in FIG. 2, a dummy element 77 should be connected to external terminals 76a, 76b and 76c of a cell 76 whose logic functions are defined as a truth table. However, this means that the existing dummy elements cannot be used for the cell 76 in a truth table form. Novel dummy elements compatible with truth table approach would have to be developed. If new dummy elements are produced case by case, the number of various types of dummy elements would be enormous. This would vastly increases the difficulty of managing or accounting for the dummy elements.
Furthermore, a method has been proposed to check for the occurrence of an error by sending the output signal of a dummy element as an "X" signal up to an external terminal of the circuit when the dummy element detects such the error. However, the cause of an error depends on the structure of each cell, requiring dummy elements designed for individual purposes. Therefore, even according to this method, the various type of dummy elements would increase dramatically, thereby complicating the management of the dummy elements.